Init-time investigation: per-stage instrumentation, bench harness, TX-ready −5s, libusb WARNING default#99
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… -5s, libusb WARNING default Investigates field reports of 20-30s init. Verdict on this rig (median of 3 cold-init reps, ch6): no 20-30s reproduces on master post-217fb76, and devourer reaches RX-ready faster than the kernel driver on every chip (8812AU 2.1s vs 3.5s, 8814AU 5.7s vs 8.4s, 8821AU 1.0s vs 3.1s). Historic reports are best explained by the pre-217fb76 pwrseq poll delay (1000x, worst case +50s) plus libusb DEBUG logging on slow sinks. - src/InitTimer.h: steady_clock stage timer, one "init-timing: <scope>.<stage> = N ms" info line per checkpoint. Checkpoints in HalModule (power-on, LLT, fwdl, EFUSE, MAC/BB/RF config, band switch, channel set), EepromManager, RadioManagementModule (sw_chnl / set_bw / tx_power / IQK), and both demos (open, reset, create, first RX frame / first TX submit). - tests/bench_init.py: cold-init benchmark per DUT — devourer RX/TX cells with A/B variants (libusb log level, skip-reset, skip-txpwr) + kernel-driver cells via the testrig VM (attach -> probe -> monitor -> first frame). - txdemo: drop the undocumented sleep(5) after InitWrite (from the original experimental TX commit). TX-ready improves exactly 5s on every chip (8812AU 6.6->1.6s, 8814AU 10.7->5.7s, 8821AU 5.9->0.9s). Full 4-cell regress matrix green at ch6 and ch36 after removal. - demo + stream_duplex_demo: libusb log level defaults to WARNING; DEBUG is opt-in via DEVOURER_USB_DEBUG=1 (was DEBUG-by-default; ~7 MB/15s stderr, +0.5-0.8s init on a fast sink, unbounded on slow ones). DEVOURER_USB_QUIET is now a no-op; regress.py no longer sets it. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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What
Investigates field reports of 20-30s init before TX/RX works, and lands the measurement infrastructure plus the two fixes the measurements confirmed.
Verdict
The 20-30s does not reproduce on current master. Historic reports are best explained by:
udelay(10)— worst-case +50s on a failing poll), andMeasured on the test rig (median of 3 cold inits, ch6, kernel cells =
aircrack-ng/88XXauin the pinned-kernel VM):Devourer now reaches ready-to-RX/TX faster than the kernel driver on every chip, both directions. The 8814's remaining 5.7s is intrinsic and kernel-faithful (EFUSE per-byte read 1.7s + BB tables 1.6s + RF tables 1.0s — USB-control-transfer-bound; the kernel pays the same or more).
Changes
src/InitTimer.h+ checkpoints inHalModule,EepromManager,RadioManagementModule, and both demos: every init logs a per-stageinit-timing: <scope>.<stage> = N msbreakdown.tests/bench_init.py: cold-init benchmark per plugged DUT — devourer RX/TX cells with A/B variants (libusb log level, skip-reset, skip-txpwr) and kernel-driver cells via the libvirt VM (attach → probe → monitor → first frame). USB port power-cycle between reps so every run is a cold init.sleep(5)afterInitWrite(undocumented settle from the original experimental TX commit). Exactly −5s TX-ready on every chip.DEVOURER_USB_DEBUG=1.DEVOURER_USB_QUIETis accepted as a no-op for old scripts.bench_init.py.Verification
sleep(5)removal.tests/bench_init.pyre-run post-fix confirms the −5s TX-ready across all three chips.🤖 Generated with Claude Code