[fpga] Fix ROM corruption on async reset assertion#649
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The async Mocha reset assertion can cause timing violations for BRAM control/address input signals, and corrupt the content of the ROM. This bug does not affect the ASIC implementation. This commit ensures both assertion and deassertion of the Mocha top reset on FPGA are synchronous to the clock, which prevents the issue.
marnovandermaas
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Great find! I was wondering about one alteration.
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| .rst_ni (ext_rst_ni & ftdi_rst_ni & fpga_rst_n_sync_cfg), | ||
| .d_i (1'b1), |
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Would this have the same effect?
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| .rst_ni (1'b1), | |
| .d_i (ext_rst_ni & ftdi_rst_ni & fpga_rst_n_sync_cfg), |
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No. Since the external reset also resets the PLL, there is a delay between reset deassertion and clocks starting to toggle. We need the external reset on the rst_ni pin to make sure the active value 0 is latched into the DFFs before the clocks start toggling.
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The asynchronous Mocha reset assertion on FPGA can cause timing violations for BRAM control/address input signals, and corrupt the content of the ROM.
This PR adds a synchroniser to ensure both assertion and deassertion of the Mocha top reset on FPGA are synchronous to the clock, which prevents this issue.
Closes #639.