Agatti fastrpc enable#754
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…d in frequency formula" This reverts commit 8e88fcf. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
This reverts commit 145cb70. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
…anaged by Linux" This reverts commit d3a21e7. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
This reverts commit 8dbe613. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
Requesting the IRQ and then immediately disabling it is fragile as it leaves a window when the IRQ is still enabled although the underlying device might be not completely setup for IRQ handling. Pass IRQF_NO_AUTOEN instead of calling disable_irq_nosync(). Link: https://lore.kernel.org/all/20260529-iris-no-autoen-v2-1-b1bbaef65b41@oss.qualcomm.com/ Fixes: fb583a2 ("media: iris: introduce host firmware interface with necessary hooks") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> [bod: Appended Fix to patch title for -stable clarity] [bod: Added cc stable for backporting] Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add support for intra refresh configuration on gen1 encoder by enabling V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD and V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE controls. Link: https://lore.kernel.org/all/20260512-batch2_features-v7-1-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add Long-Term Reference(LTR) frame support for both gen1 and gen2 encoders by enabling the following V4L2 controls: V4L2_CID_MPEG_VIDEO_LTR_COUNT V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX Link: https://lore.kernel.org/all/20260512-batch2_features-v7-2-4954e3b4df84@oss.qualcomm.com/ Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add support for B-frame configuration on both gen1 and gen2 encoders by enabling V4L2_CID_MPEG_VIDEO_B_FRAMES control. Link: https://lore.kernel.org/all/20260512-batch2_features-v7-3-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add hierarchical coding support for both gen1 and gen2 encoders by enabling the following V4L2 controls: H264: V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING, V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE, V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER HEVC(gen2 only): V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER Link: https://lore.kernel.org/all/20260512-batch2_features-v7-4-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…_property Modify iris_hfi_gen1_packet_session_set_property to simplify size calculations and remove redundant code patterns. Previously, packet->shdr.hdr.size was incremented by sizeof(u32) in every switch case, resulting in repetitive and less maintainable logic. Link: https://lore.kernel.org/all/20260512-batch2_features-v7-5-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Unify AVC/HEVC handling by computing codec and lcu_size upfront. Link: https://lore.kernel.org/all/20260512-batch2_features-v7-6-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…uency formula The driver was using a fixed default FPS value when calculating the VPU frequency. This caused wrong frequency requests for high‑frame‑rate streams, for example 4K at 240 FPS. Because of this, the hardware was running at a lower frequency than needed. Add the FPS measurement based on the decoder input buffer arrival rate. The measured FPS is stored per instance and used in frequency calculation instead of the fixed default FPS. The value is clamped so that it does not exceed platform limits. Add a VPP firmware overhead when running in STAGE_2. Link: https://lore.kernel.org/all/20260401-update_fps_calculation-v6-1-f44f8154ca39@oss.qualcomm.com/ Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…PU4x The existing iris_vpu_dec_comv_size() used VIDEO_MAX_FRAME (32) as num_comv count unconditionally when calculating the co-located motion vector (COMV) buffer size. This resulted in an oversized COMV buffer allocation throughout decode session, wasting memory regardless of actual number of buffers required. For VPU3x and VPU4x platforms, introduce iris_vpu3x_4x_dec_comv_size() to replace iris_vpu_dec_comv_size(). These derive num_comv dynamically, it uses inst->fw_min_count once the firmware has reported its buffer requirements, and fallback to output count during initialization before firmware has communicated its requirements. This aligns the COMV buffer size to the actual count needed rather than always allocating with fixed VIDEO_MAX_FRAME value. Additionally, during iris_vdec_inst_init(), fw_min_count was initialized to MIN_BUFFERS instead of 0. This masked the fallback logic and caused the COMV size calculation to use MIN_BUFFERS even before firmware had reported its actual requirements. Fix this by initializing fw_min_count to 0. During testing of 1080p AVC, it reduces the COMV buffer size from 32.89MB to 6.16MB per decode session, significantly reducing memory consumption. Link: https://lore.kernel.org/all/20260514-optimize_comv_buffer-v4-1-7da70b586aec@oss.qualcomm.com/ Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
On X1P42100 the Iris block has an extra BSE clock. Wire this clock into the power on/off sequence. The BSE clock is used to drive the Bin Stream Engine, which is a sub-block of the video codec hardware responsible for bitstream-level processing. It is required to be enabled separately from the core clock to ensure proper codec operation. Link: https://lore.kernel.org/all/20260529-enable_iris_on_purwa-v8-2-b1b9670459ab@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Introduce platform data for X1P42100, derived from SM8550 but using a different clock configuration and a dedicated OPP setup. Link: https://lore.kernel.org/all/20260529-enable_iris_on_purwa-v8-3-b1b9670459ab@oss.qualcomm.com/ Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
The struct iris_fmt unites pixfmt with the plane type, however the type from the struct is not actually used. Drop the struct completely and use u32 pixfmt in all the callsites. Link: https://lore.kernel.org/all/20260529-iris-remote-fmts-v7-1-a8bd57ac8b5a@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…init The HFI sys ops were previously initialized in probe() but, we don't have firmware loaded at probe time. Since HFI is tightly coupled to firmware, initialize the HFI sys ops after firmware has been successfully loaded and booted. Link: https://lore.kernel.org/all/20260529-kodiak-gen2-support-v4-v6-1-9a81bfa797d9@oss.qualcomm.com/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Use div_u64() instead of mult_fract as u64 operator division fails on 32 bit systems which don't link against libgcc. Link: https://lore.kernel.org/all/20260602-fixbranch-v1-1-b8eccaad6d17@kernel.org/ Fixes: 5c66647a5c3e ("media: iris: add FPS calculation and VPP FW overhead in frequency formula") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202606030132.qnBXVDkM-lkp@intel.com/ Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
To simplify code checking for pixel formats, add helpers to check for 8bit and 10bit formats. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-1-c2b32474ed67@linaro.org/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
The P010 (YUV format with 16-bits per pixel with interleaved UV) and QC10C (P010 compressed mode similar to QC08C) requires specific buffer calculations to allocate the right buffer size for the DPB (decoded picture buffer) frames and frames consumed by userspace. Similar to 8bit, the 10bit DPB frames uses QC10C format. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-2-c2b32474ed67@linaro.org/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add the necessary plumbing into the HFi Gen2 to signal the decoder the right 10bit pixel format and stride when in compressed mode. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-3-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
… for 10bit formats Update the gen2 response and vdec s_fmt code to take in account the P010 and QC010 when calculating the width, height and stride. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-4-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…nd 10bit formats The 10bit pixel format can be only used when the decoder identifies the stream as decoding into 10bit pixel format buffers, so update the find_format helper to filter the formats and only allow the proper formats when setting or trying a capture format. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-5-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add the necessary bits into the gen2 platforms tables and handlers to allow decoding streams into 10bit pixel formats. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-6-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Some Iris platforms support both Gen1 and Gen2 HFI firmware images. Update the firmware loading logic to handle this generically by preferring Gen2 when available, while safely falling back to Gen1 when required. The firmware loading logic is updated with the following priority: 1. Device Tree (`firmware-name`): If specified, load unconditionally. 2. Gen2 default : If no DT override exists, select the Gen2 firmware descriptor when present and attempt to load the corresponding firmware image. 3. Gen1 Fallback: If loading the Gen2 firmware fails and a Gen1 descriptor is available, retry with the Gen1 firmware image. When a platform provides both Gen1 and Gen2 firmware descriptors and the firmware is loaded via a DT override, the driver detects the firmware generation at runtime before authentication by inspecting the firmware data. The firmware is classified as Gen2 if the QC_IMAGE_VERSION_STRING starts with "vfw" or matches the "video-firmware.N.M" format with N >= 2. If a Gen1 firmware image is detected in this case, the driver switches to the Gen1 firmware descriptor and associated platform data so that the correct HFI implementation is used. This change makes firmware generation detection platform‑agnostic, preserves DT overrides, prefers newer Gen2 firmware when available, and maintains compatibility with platforms that only support Gen1. Link: https://lore.kernel.org/all/20260529-kodiak-gen2-support-v4-v6-2-9a81bfa797d9@oss.qualcomm.com/ Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Co-developed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
UBWC configuration is not applicable to all SoCs. Add a check to avoid configuring UBWC during sys init on unsupported platforms. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-1-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
…bilities The raw formats supported by Iris were previously advertised unconditionally, assuming UBWC support on all platforms. However, some platforms do not support UBWC which results in incorrect format capability exposure. Use the UBWC configuration provided by the platform to dynamically filter raw formats at runtime. If UBWC is not supported, UBWC-based formats are omitted from the advertised capability list, while linear formats remain available. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-2-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
The set_preset_registers sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move set_preset_register into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-3-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
The interrupt_init sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move interrupt_init into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-4-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
On AR50LT platforms AbsolutelyPerfectRouting (ARP) needs to be disabled so firmware can configure the ARP internal buffer as non-secure for encoder usage. In preparation of adding support for AR50LT platforms, add an optional disable_arp callback to the VPU ops and invoke it from core init and resume paths. No functional change for existing platforms. Link: https://lore.kernel.org/all/20260515-iris-ar50lt-v3-5-df3846e74347@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
# Conflicts: # arch/arm64/boot/dts/qcom/lemans.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/monaco.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/kaanapali.dtsi
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/qcs8300-ride.dts # drivers/bluetooth/hci_qca.c # drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
# Conflicts: # Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml # drivers/gpu/drm/bridge/lontium-lt9611c.c # drivers/misc/fastrpc.c # drivers/remoteproc/qcom_q6v5_pas.c # drivers/soc/qcom/smem.c # sound/soc/qcom/qdsp6/q6prm.h
Add IPCC_CLIENT_RTSS0/1/2/3 client ID definitions (27-30) to the qcom-ipcc dt-bindings header for use by the RTSS Mailbox device tree overlay. Signed-off-by: Sankalp Negi <snegi@qti.qualcomm.com>
Add lemans-rtss-mb.dtso overlay for Lemans platform providing: - ipcc_computeL1: IPCC Compute-L1 controller - rtss_mailbox: RTSS Mailbox device node. Signed-off-by: Sankalp Negi <snegi@qti.qualcomm.com>
Add monaco-rtss-mb.dtso overlay for Monaco platform providing: - ipcc_computeL1: IPCC Compute-L1 controller - rtss_mailbox: RTSS Mailbox device node. Signed-off-by: Sankalp Negi <snegi@qti.qualcomm.com>
Adding glymur-crd to the QSEECOM allowlist causes qcom_scm to fully initialize at early boot, which sets up uefisecapp and registers EFI variable operations. This makes efi_has_tpm2() succeed by reading the LoaderTpm2ActivePcrBanks EFI variable, satisfying ConditionSecurity=tpm2 in systemd. As a result, systemd activates tpm2.target which unconditionally waits for /dev/tpm0 and /dev/tpmrm0. systemd waits the full 90-second timeout for each of the two TPM device units, pushing total boot time beyond 2 minutes. Revert until TPM driver in place and /dev/tpm0 node is created. This reverts commit 87a1698. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…g/pub/scm/linux/kernel/git/torvalds/linux.git tech/bsp/clk d278a36 18 tech/bsp/devfreq a0c2f21 6 tech/bsp/ec 643c24b 2 tech/bsp/soc-infra 6aff3e6 25 tech/bsp/pinctrl 3f1acf8 1 tech/bsp/remoteproc a7b9b6d 10 tech/bus/peripherals 342d00a 10 tech/bus/pci/all 7650854 26 tech/bus/pci/phy aaf8ef1 4 tech/bus/usb/dwc e929e6d 3 tech/bus/usb/phy 984aa89 36 tech/debug/hwtracing 25c6a74 30 tech/pmic/misc ee32a8c 5 tech/mem/iommu 2831e57 7 tech/mm/audio/all cab3357 10 tech/mm/camss fdc4e57 34 tech/mm/drm 24ebe66 62 tech/mm/fastrpc 7cd5e18 13 tech/mm/video 1bc33f6 166 tech/mm/gpu f67b888 6 tech/net/ath edebe42 20 tech/net/phy a3602e9 1 tech/pm/power 2d42c35 9 tech/pm/thermal 3f033cb 7 tech/security/crypto f030676 14 tech/security/ice c72a252 18 tech/storage/all 6a34168 4 tech/all/dt/qcs6490 abb8a3a 22 tech/all/dt/qcs9100 fe7da88 23 tech/all/dt/qcs8300 c8a238b 23 tech/all/dt/qcs615 277da5d 11 tech/all/dt/agatti c828f10 1 tech/all/dt/hamoa f070434 31 tech/all/dt/glymur 7712b84 35 tech/all/dt/kaanapali 0fa62a7 15 tech/all/dt/pakala d7f29fa 9 tech/all/config a370d20 68 tech/overlay/dt 587d3d5 60 tech/all/workaround f3ee72b 24 tech/mproc/all 0aa90b7 3 tech/noup/debug/all cbdd4bb 26 tech/hwe/unoq b2ea57b 5 early/hwe/shikra/drivers bd708fc 168 early/hwe/shikra/dt 95e145f 107
…y DSF On Shikra, the DDR System Firmware (DSF) configures ECC interrupt routing before the kernel driver probes — it enables Tag/Data RAM interrupts and programs error thresholds in the LLCC interrupt-enable registers. Set irq_configured in shikra_cfg so that qcom_llcc_edac_probe() skips calling qcom_llcc_core_setup(), which would otherwise overwrite the firmware-managed register state with redundant writes. Signed-off-by: Faiyaz Mohammed <faiyazm@qti.qualcomm.com>
…blement The eMMC overlay currently explicitly overrides the vreg_l8a voltage to handle the common VDD rail shared between UFS and eMMC. However, their mutual exclusivity is now managed dynamically via DT-fixup logic. Remove these static entries from the overlay to allow flexible storage configurations. Link: https://lore.kernel.org/all/20260616130347.3096034-1-monish.chunara@oss.qualcomm.com/ Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
This reverts commit b2ea57b. RB1 board able to boot up with this change https://lore.kernel.org/all/20260609025938.457-1-jianping.li@oss.qualcomm.com/ Signed-off-by: Mahima Bhattaram <mbhattar@qti.qualcomm.com>
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Reapply "arm64: dts: qcom: agatti: enable FastRPC on the ADSP"