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fpga-development

Here are 17 public repositories matching this topic...

sdnellen / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design

Updated Jun 25, 2026
Verilog

firesim / aws-fpga-firesim

AWS Shell for FireSim

fpga aws-ec2 fpga-development aws-fpga

Updated Nov 13, 2024
VHDL

arnav-gudibande / fpga-intro-guide

Introductory guide to building and programming FPGAs

fpga hdl modelsim quartus-prime quartus fpga-development

Updated Aug 3, 2017
Tcl

zhangym0115 / Vflux

A lightweight graphical FPGA development workflow tool built around OSS CAD Suite.

fpga desktop-application icestorm yosys ice40 fpga-development verilog-project nextpnr nextpnr-ice40 nextpnr-ecp5 icesugar oss-cad-suite

Updated May 8, 2026
JavaScript

alexeykosinov / UT8QNF8M8-Controller

UT8QNF8M8 NOR Flash Controller VHDL Module

vhdl fpga-firmware fpga-development aeroflex ut8qnf8m8 nor-flash

Updated Jan 14, 2019
VHDL

Strato75 / FPGACorrelator

FPGA backend correlator for the microwave holography system installed on the Sardinia Radio Telescope (SRT)

python fpga backend verilog srt radioastronomy sardinia fpga-development correlator sardinia-radio-telescope microwave-holography

Updated Mar 26, 2020
Verilog

accemic / abc-flow

Text-based dependency files for FPGA projects.

hdl fpga-development

Updated Jun 11, 2026
Shell

Preven-K / Vending-Machine

Verilog-based vending machine controller IP core, supporting multi-clock domain operation, inventory management, and currency denominations. Built with the APB protocol for efficient configuration, it offers smart change calculation and robust error handling. Developed in the SURE ProEd internship training with experts.

embedded-systems error-handling verilog memory-management vlsi digital-systems fpga-development vlsi-design hardware-design internship-project apb-protocol sure-trust vending-machine-controller sure-proed multi-clock-domain

Updated Apr 25, 2025
Verilog

AZsnake / sensor-test-framework-s2c

S2C VP1902 FPGA MIPI CSI-2 验证框架（纯 RTL）：Versal PDI + PPro-RT8 + PySide6，2-Lane RAW10（IMX298）

Updated Jul 6, 2026
Verilog

erfan-nourbakhsh / MatrixForge

A high-performance VHDL coprocessor for 3×3 matrix multiplication with FSM control unit and optimized processing pipeline

vhdl digital-systems fpga-development matrix-operations hardware-design

Updated Aug 19, 2025
VHDL

panktipatel1711 / VLSI-Digital-Clock-Alarm

A parameterizable and synthesizable single-clock-domain Digital Clock core with integrated Alarm, Snooze, and 12/24-hour display modes implemented in Verilog HDL. Features double-register button debouncing and a time-multiplexed 7-segment display driver.

verilog systemverilog testbench digital-clock digital-design hardware-description-language fpga-development vlsi-design rtl-design fsm-controller

Updated Jun 21, 2026
Verilog

AZsnake / sensor-test-framework-soft-core

VU13P FPGA MIPI CSI-2 验证框架（MicroBlaze）：Vivado BD + Vitis 固件 + PySide6，2-Lane RAW10（IMX298）

Updated Jun 26, 2026
Python

oluwaferanmi-arowoshola / microblaze-embedded-system

MicroBlaze FPGA embedded system on Nexys DDR using Vivado/Vitis, AXI GPIO peripherals, UART, and C firmware for memory-mapped switch-to-LED hardware control.

c fpga embedded-systems xilinx vivado uart xilinx-fpga digital-design embedded-c microblaze fpga-development vitis memory-mapped-io hardware-software-integration soft-core-processor board-validation axi-gpio nexys-ddr

Updated May 16, 2026
C

AZsnake / sensor-test-framework-pure-rtl

VU13P FPGA MIPI CSI-2 验证框架（纯 RTL）：Vivado BD + mipi_sys_ctrl + PySide6，2-Lane RAW10（IMX298）

python fpga camera rtl verilog xilinx vivado uart hardware-testing fpga-development mipi csi-2 pyside6 bring-up sensor-validation xilinx-ultrascale imx298 vu13p sensor-test-framework

Updated Jun 26, 2026
Verilog

AZsnake / adda-test-framework

VU13P FPGA ADDA 调试与验证框架：UART/SPI boot、ADC IQ DSP、DAC 2× DDR、PySide6（SI5340 / AD9640 / AD9117）

Updated Jun 26, 2026
Verilog

karimzakzouk / AES

Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.

security cryptography fpga aes-256 aes-128 aes-192 aes-encryption verilog-hdl data-encryption data-security advanced-encryption-standard aes-decryption fpga-development algorithm-implementation hardware-design

Updated May 14, 2024
Verilog

winfieldmassspectroscopic818 / Vflux

Visualize and manage your OSS CAD Suite FPGA design workflow through a simple graphical interface.

fpga desktop-application isotope icestorm yosys ice40 fpga-development verilog-project react-snap nextpnr nextpnr-ice40 nextpnr-ecp5 icesugar oss-cad-suite

Updated Jul 19, 2026
JavaScript

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