FROMLIST: arm64: dts: qcom: shikra: fix interrupt specifier cell count#751
FROMLIST: arm64: dts: qcom: shikra: fix interrupt specifier cell count#751apateriy-qcom wants to merge 1 commit into
Conversation
The GIC v3 binding requires four cells per interrupt specifier: <type number flags affinity>. Five device nodes in shikra.dtsi used only three cells, omitting the required CPU affinity cell: - PCIe MSI interrupts (GIC_SPI 491-498, 489) - SDHC slot 2 (GIC_SPI 350, 353) - GPI DMA0 (GIC_SPI 511-526) - ethernet0 / EMAC0 (GIC_SPI 478) - ethernet1 / EMAC1 (GIC_SPI 458) Link: https://lore.kernel.org/all/20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com/ Link: https://lore.kernel.org/all/20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com/ Signed-off-by: Shiraz Hashim <shiraz.hashim@oss.qualcomm.com>
Test Matrix
|
|
Ack for the ethernet fix. Thanks for raising this. |
PR #751 — validate-patchPR: #751
Final Summary
|
PR #751 — checker-log-analyzerPR: #751
Detailed report: Full report
|
|
@apateriy-qcom please check dtb-check failure : |
For Shikra, interrupt cell count required is 4, GPI DMA has to be handled to use 4 interrupts cells. |
The GIC v3 binding requires four cells per interrupt specifier: . Five device nodes in shikra.dtsi used only three cells, omitting the required CPU affinity cell:
Link: https://lore.kernel.org/all/20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com/
Link: https://lore.kernel.org/all/20260608-shikra-dt-m1-v4-0-2114300594a6@oss.qualcomm.com/
CRs-Fixed: 4580054